How to Make an H100 - Manuel Arce

Understanding GPUs

Architecture generations define the GPU model. When we talk about the H100, we're referring to NVIDIA's Hopper architecture—but what exactly does that mean?

The Hopper Architecture defines the name H100. But when we say "an H100 GPU," what exactly are we referring to?

There are two main variants of this GPU: the PCIe-based and the HGX-based. Each serves different markets and use cases, from individual servers to massive AI training clusters.

Architecture Generations

Generation	Year	Example GPUs	Key Innovations
Volta	2017	V100	First Tensor Cores, HBM2 memory
Turing	2018	RTX 2080, T4	Real-time ray tracing, INT8/INT4 inference
Ampere	2020	A100, RTX 30 series	3rd-gen Tensor Cores, HBM2e, PCIe 4.0
Hopper	2022	H100	Transformer Engine, HBM3, NVLink 4.0
Blackwell	2025	B100, B200	Faster interconnects, FP8 AI support

H100 Variants

The H100 comes in several form factors, each optimized for different deployment scenarios. Understanding these variants is crucial for matching hardware to workloads.

Family	Variant	Form Factor	Memory	Power (TDP)	Best For
PCIe-based	H100 PCIe	PCIe Gen5 x16 card	80 GB HBM3	~350-400W	General AI, smaller training
	H100 NVL	Dual-GPU PCIe board	94 GB HBM3	~600-700W total	LLM inference, high VRAM
	H100 CNX	PCIe + ConnectX-7 NIC	80 GB HBM3	~350-400W	Multi-node AI, low-latency
HGX-based	H100 SXM5	SXM5 module for HGX	80 GB HBM3	700-900W	Large-scale AI training

SXM & HGX Platform

SXM (Server eXpress Module) is a socketed GPU module used in high-end servers. The SXM5 variant is designed specifically for data center deployment—it sits flat on a large connector on a specialized baseboard.

The SXM module integrates:

The GPU die itself
HBM3 memory stacks
Power delivery circuitry

All on a compact board that allows direct NVLink lanes between GPUs without routing through the CPU or PCIe bus.

You plug the SXM module into a specialized GPU baseboard called the HGX board—a motherboard built exclusively for GPUs.

HGX is NVIDIA's server motherboard platform for multiple SXM GPUs plus NVSwitches. This board doesn't have a CPU or system RAM—just sockets (SXM slots) for GPUs and NVSwitch chips to link them together.

There are two main variations:

HGX with 4 SXM slots
HGX with 8 SXM slots

The HGX connects to the main system board using high-speed board-to-board links and cables. While NVIDIA designs the board, it ships through OEM partners like Dell, Supermicro, and Inspur.

PCIe Variants

PCIe (Peripheral Component Interconnect Express) is the standard expansion card interface used in normal motherboards. PCIe-based H100s are the more accessible option—they slot into standard server infrastructure.

H100 NVL is a special dual-GPU variant designed for large language model (LLM) inference. It prioritizes huge memory capacity per GPU and super-fast GPU-to-GPU communication over absolute maximum training performance.

H100 CNX combines an H100 PCIe with a Mellanox ConnectX-7 network adapter on the same PCB. This addresses a critical bottleneck in distributed training:

CNX skips that hop by having the network chip connected directly to GPU memory via RDMA—GPUs in different servers need to exchange data every few milliseconds during training.

The slowest part of multi-node training is typically the extra hop through the CPU and PCIe bus. CNX eliminates this latency by co-locating the network interface.

Understanding the H100 Die

The heart of the H100 is the GH100 die—the small rectangular piece of silicon at the center of the package. This die is cut from a wafer manufactured by TSMC.

flowchart TD
    A[H100 GPU Variants] --> B[PCIe-based]
    A --> C[HGX-based]

    B --> D[H100 PCIe
80 GB HBM3
~350-400W TDP]

    B --> E[H100 NVL
94 GB HBM3
~600-700W total]

    B --> F[H100 CNX
80 GB HBM3
+ ConnectX-7 NIC]

    C --> G[H100 SXM5
80 GB HBM3
700-900W TDP]

    classDef familyBox fill:#ff6b00,stroke:#ff6b00,stroke-width:2px,color:#fff
    classDef variantBox fill:#2a2a2a,stroke:#ff6b00,stroke-width:1px,color:#fff
    classDef rootBox fill:#1a1a1a,stroke:#ff6b00,stroke-width:3px,color:#ff6b00

    class A rootBox
    class B,C familyBox
    class D,E,F,G variantBox

Manufacturing Process: The H100 uses TSMC's N4 process (4nm node). While the exact wafer specifications aren't publicly documented, 5nm and 4nm chips are manufactured on 300mm (12-inch) wafers.

Die Specifications:

Die size: approximately 814 mm²
Transistor count: 80 billion
Process: TSMC 4N (optimized 5nm)

The specific substrate grade and crystal growth method details aren't publicly documented. The wafers are likely prime-grade 300mm silicon wafers grown using the Czochralski process, but finding direct confirmation proves difficult.

Raw Wafer Suppliers

TSMC's 2023 annual report lists their raw wafer suppliers:

1

FST

Formosa Sumco

2

GlobalWafers

Taiwan/US

3

SEH

Shin-Etsu

4

Siltronic

Germany

5

SK Siltron

South Korea

6

SUMCO

Japan

While we know TSMC's suppliers, we don't know which specific companies supply the wafers used for H100 production, or even which fab within TSMC's network produces them (though Fab 18 in Tainan is the primary 5nm/4nm facility).

Spruce Pine, North Carolina, USA... responsible for 70 to 90% of the global semiconductor-grade quartz.

Component Analysis

The H100 module requires components from across the globe. Here are the key Tier 1 components:

Component	Supplier	Facility & Location	Confidence
GH100 GPU Die (TSMC 4N)	TSMC	Fab 18, Tainan, Taiwan	Confirmed
HBM3 Memory Stack	SK Hynix	M16 DRAM Fab, Icheon, S. Korea	High
CoWoS Silicon Interposer	TSMC / UMC	TSMC Advanced Packaging	Moderate
Package Substrate (FC-BGA)	Ibiden Co., Ltd.	Ogaki Plant, Gifu, Japan	High

Component Tiering System:

0

Final Assembly

NVIDIA H100 SXM5 Module

1

Core Silicon & Packaging

GPU Die, HBM3 Stacks, CoWoS Interposer, Package Substrate

2

Board-Level Active Components

VRM/Power Stages, PMICs, MCUs, PCIe Retimers

3

PCB & Connectors

Main Circuit Board, High-Density Connectors

4

Mechanical & Thermal

Vapor Chamber, Heatsink, Stiffening Bracket, TIM

5

Passives & Other

MLCCs, Inductors, Resistors, Crystals

6

Upstream Materials

Wafers, Leadframes, Epoxy, ABF Film, Solder

7

Process Consumables

Gases, Slurries, Photoresists, Solvents

8

Raw Materials

Silicon Metal, Copper Ore, Crude Oil, Lithium Brine

Silicon Manufacturing

The journey from raw materials to finished wafer involves multiple complex steps spanning continents.

Raw Quartz (Silica Sand)

Even though silicon dioxide is one of the most abundant minerals on Earth, semiconductor-grade material must be of extremely high purity with very low trace metals.

Spruce Pine, North Carolina—where workers mine quartz from the mountains—is responsible for 70 to 90% of the global semiconductor-grade quartz supply.

Metallurgical-Grade Silicon

Quartz is carbothermically reduced in an electric arc furnace (at ~1500-2000°C) with carbon to produce metallurgical-grade silicon (≈96-99% silicon).

Polysilicon via the Siemens Process

That silicon is further purified via the Siemens chemical-vapor-deposition process into electronic-grade polysilicon (≥99.999999% pure). Alternatives like fluidized-bed reactor processes exist, but Siemens remains dominant.

Growing Single-Crystal Ingots (Czochralski Process)

Polysilicon is melted in a high-purity quartz crucible at about 1425°C. A seed crystal is dipped into the molten silicon, then slowly pulled upward and rotated to grow a single-crystal cylindrical ingot (boule).

Precise control of temperature, rotation, and pull rate is essential to yield a defect-free monocrystal. Controlled amounts of dopants like boron or phosphorus can be added during growth to set resistivity.

Wafer Slicing and Polishing

Ingot Conditioning: The ingot's circumference is ground to a uniform diameter and ends trimmed to ensure crystal orientation and stability.

Slicing: Using diamond-coated wire saws, the ingot is sliced into ~1mm thick wafers.

Lapping and Grinding: Wafers are ground and polished using alumina abrasives to reach target thickness and flatness specifications.

Polishing: Chemical-mechanical polishing (CMP) removes surface damage, achieving mirror-smooth, planar wafers ready for fabrication.

Epitaxial Layer (Optional)

For applications requiring ultra-uniform doping, wafers undergo epitaxial deposition. In a furnace (~1200°C), gases like trichlorosilane (SiHCl₃) are introduced to grow a crystalline silicon film atop the wafer surface.

Inspection, Packaging & Shipping

Finished wafers undergo stringent quality control: flatness, thickness tolerance, resistivity, defect density, and micro-contamination testing.

Passing wafers are clean-room packed in FOUPs (Front Opening Unified Pods), then shipped—typically by air freight under climate-controlled, vibration-damped conditions—to fabs such as TSMC in Taiwan.

Refiner	Location	Supplies To	Likely Quartz Source
Tokuyama Corporation	Japan	SUMCO (Yonezawa, JP)	Spruce Pine + others
Mitsubishi Materials	Japan	SUMCO	Spruce Pine / global HPQ
Wacker Chemie	Germany / USA	SUMCO, GlobalWafers	Spruce Pine (via Sibelco)
Hemlock Semiconductor	Michigan, USA	GlobalWafers, SUMCO	Spruce Pine quartz
OCI	South Korea	GlobalWafers	Spruce Pine, others

The H100 represents one of humanity's most complex manufactured objects—a product of global supply chains, decades of research, and processes operating at the atomic scale.

How to Make an H100.